1. Field of the Invention
The present invention relates generally to memory cells, arrays and devices and, in particular, to improvement of a refresh margin in a DRAM memory device.
2. State of the Art
Memory devices are typically provided as internal storage areas in a computer. There are several different types of memory, one of which is known as random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, meaning it requires a periodic regeneration of stored electrical charge to maintain its contents. A dynamic random access memory (DRAM) is a type of RAM that is made up of cells wherein each cell or bit includes one or more transistors and capacitors. A cell is capable of storing information in the form of a “1” or “0” bit as an electrical charge on the capacitor. Since a capacitor will lose its charge over time, a memory device incorporating a DRAM cell must include logic to refresh or recharge the capacitors of the cells on a periodic basis. Otherwise, the information stored therein will fade and be lost. One form of refreshing or recharging the capacitor is performed by reading the stored data in a memory cell and then writing the data back into the cell at a predefined voltage level, causing the information to be stored for a temporary period of time.
More specifically, a conventional 2T DRAM array 10 shown in FIG. 1 stores digital information in the form of “1” and “0” bits by storing the bits as electric charges on storage capacitors 38, 40 in a first memory cell and capacitors 48, 50 in a second memory cell as arranged along wordlines WL0 56 and WL1 58. For clarity, a single 2T memory cell 20 is depicted in an upper portion of the DRAM array 10 and is shown to include two capacitors (2C) and two transistors (2T) and is coupled to a sense amplifier 24 when isolation gates 30, 32 are activated by a sense amp isolation signal 26. Furthermore, while DRAM array 10 is illustrated as including only eight memory cells in order to simplify description, the DRAM array 10 typically includes thousands or millions of memory cells.
The DRAM array 10 stores a “1” bit in an exemplary memory cell, for example, the memory cell comprised of pass transistor 36, storage capacitors 38, 40 and pass transistor 42, by initially energizing the wordline WL0 56 to activate the pass transistors 36, 42. The DRAM array 10 then applies a “1” bit voltage equal to a supply voltage Vcc (e.g., 3.3 volts) to the true D0 digit line 16, causing current to flow from the digit line 16 via connection 54 through the activated pass transistor 36 and the storage capacitor 38 to a cell plate voltage 34. As the current flows, the storage capacitor 38 stores positive electric charge received from the digit line 16, causing a voltage on the storage capacitor 38 to increase. When the voltage on the storage capacitor 38 equals the “1” bit voltage on the digit line 16, current stops flowing through the storage capacitor 38. Similarly, energizing the wordline WL0 56 also activates the pass transistor 42. The DRAM array 10 then applies a “0” bit voltage equal to Vss (e.g., 0 volts) to the complementary D0* digit line 18 causing current to flow from the cell plate voltage 34 to the storage capacitor 40. As the current flows, the storage capacitor 40 stores positive electric charge received from the cell plate voltage 34. A short time later, the DRAM array 10 deenergizes the wordline WL0 56 to deactivate the pass transistors 36, 42 and isolate the storage capacitors 38, 40 from the digit lines 16, 18, thereby preventing the positive electric charge stored on the storage capacitors 38, 40 from discharging back to the digit lines 16, 18.
Similarly, the DRAM array 10 stores a “0” bit in a memory cell, for example, by energizing the wordline WL0 56 to activate the pass transistors 36, 42 and applies a “0” bit voltage approximately equal to a reference voltage Vss (e.g., 0.0 volts) to the digit line 16, causing current to flow from the cell plate voltage 34 to the storage capacitor 38 and the activated pass transistor 36 and to the true D0 digit line 16. As the current flows, storage capacitor 38 stores electric charge received from the cell plate voltage 34 causing the cell plate voltage 34 to be stored in a negative polarity in storage capacitor 38. Similarly, the pass transistor 42 is also activated and causes the “1” bit voltage on complementary D0* digit line 18 to flow through pass transistor 42 and be stored in a negative polarity in storage capacitor 40. The voltage stored across storage capacitor 40 is approximately equal to the supply voltage Vcc minus the cell plate voltage 34. When the voltage across storage capacitors 38, 40 stabilizes, current stops flowing through the storage capacitors 38, 40 and a short time later the DRAM array 10 deenergizes the wordline WL0 56 to deactivate the pass transistors 36, 42 and isolate the storage capacitors 38, 40 from the digit lines 16, 18, thereby preventing the stored electrical charge on the storage capacitors 38, 40 from discharging back to the digit lines 16, 18.
The DRAM array 10 retrieves “1” and “0” bits stored in the manner described above in a memory cell by discharging the electric charges stored on the storage capacitors 38, 40 to the digit lines 16, 18 and then detecting a change in voltage on the digit lines 16, 18 resulting from the discharge with the sense amplifier 22 when isolation gates 30, 32 are activated by a sense amp isolation signal 26.
For example, the DRAM array 10 retrieves the “1” bit stored in the memory cell by first equilibrating the voltages on the digit lines 16, 18 to the cell plate voltage 34. The DRAM array 10 then energizes the wordline WL0 56 to activate the pass transistors 36, 42, causing the positive electric charge stored on the storage capacitor 38 to discharge through the active pass transistor 36 and negative electrical charge stored on the storage capacitor 40 to discharge through the active pass transistor 42 to the digit lines 16, 18. As a positive electric charge discharges, the voltage on the digit line 16 rises and the voltage on the digit line 18 decreases, causing a differential voltage between digit line 16 and digit line 18 as detected at sense amplifier 22. When a differential voltage between the digit lines 16 and 18 exceeds a detection threshold of the sense amplifier 22, the sense amplifier 22 responds by driving the voltage of the digit line 16 to the supply voltage Vcc and by driving the voltage on the digit line 18 approximately to the reference voltage Vss and the detection of a “1” bit from the memory cell is completed.
Likewise, the DRAM array 10 retrieves the “0” bit stored in the memory cell, for example, by first equilibrating the voltages on the digit lines 16 and 18 to the cell plate voltage 34. The DRAM array 10 then energizes the wordline WL0 56 to activate the pass transistors 36, 42 causing the negative electric charge stored in the storage capacitors 38, 40 to discharge through the activated pass transistors 36, 42 and positive electrical charge stored on the storage capacitor 40 to discharge through the active pass transistor 42 to the digit lines 16 and 18. As the negative electric charge discharges, the voltage on the digit line 16 decreases below the cell plate voltage 34 and the voltage on digit line 18 increases above the cell plate voltage 34 causing a difference in voltages between digit lines 16 and 18 to exceed a detection threshold of the sense amplifier 22 causing the sense amplifier 22 to respond accordingly by driving the voltage on the digit lines 16, 18 to the appropriate voltages, namely, driving the voltage on digit line 16 to the reference voltage Vss and the voltage on the digit line 18 to the supply voltage Vcc.
While an ideal configuration of a DRAM array has been described for storing and retrieving the logic states that were originally stored therein, DRAM arrays sometimes contain defective memory cells which cause the stored logic states to become undetectable or at least intermittently unreliable. In some instances, this occurs because the capacitance of the storage capacitors in these memory cells are too small, preventing the capacitors from retaining a sufficient electric charge to cause a change in the sensing voltage on the digit line when discharged to the digit line, such as in the case when the discharged voltage does not adequately influence the equilibrated digit lines in such a manner as to cause the sense amplifier's detection threshold to be reached. In other instances, memory arrays and their corresponding memory cells may be defective because the electric charge stored on the storage capacitors in such memory cells leaks away through a variety of mechanisms which also prevents the capacitors from retaining a sufficient electric charge to cause a detectable change in the threshold voltage on the digit lines when the storage capacitors are discharged to the digit lines. In either case, because the change in the sensed voltage caused by the discharging of the storage capacitors cannot be detected by the sense amplifier, the “1” and “0” bits represented by the electric charges stored in the memory cells are unretrievable.
With respect to FIG. 1, the presence of a cell plate voltage 34 between the charges stored across storage capacitors 38 and 40 may deviate unequally if the cell plate voltage 34 is held to a constant voltage. For example, if a “1” bit is stored across a memory cell, a voltage potential approximately equal to Vcc minus the cell plate voltage 34 is stored across storage capacitor 38. Similarly, a voltage of approximately the cell plate voltage 34 minus the reference voltage Vss is stored across storage capacitor 40. If storage capacitor 38 is defective and leaks a portion of the charge stored therein, the overall loss in stored charge is reflected only across the voltage as presented to digit line 16 during a sense operation. Accordingly, the charge coupled to digit line 16 during a sense operation may not be sufficient to exceed a sensing threshold during the sense operation. Similarly, any leakage on storage capacitor 40 would result solely in a change to the voltage as coupled to digit line 18 during a sense operation. Therefore, there is a need for an improved memory cell configuration for storing therein digit information that is less susceptible to a single defective storage capacitor.